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Espressif Systems /ESP32-P4 /H264_DMA /IN_CONF0_CH5

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Interpret as IN_CONF0_CH5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IN_ECC_AES_EN_CH5)IN_ECC_AES_EN_CH5 0IN_MEM_BURST_LENGTH_CH5 0 (IN_PAGE_BOUND_EN_CH5)IN_PAGE_BOUND_EN_CH5 0 (IN_RST_CH5)IN_RST_CH5 0 (IN_CMD_DISABLE_CH5)IN_CMD_DISABLE_CH5

Description

RX CH5 config0 register

Fields

IN_ECC_AES_EN_CH5

When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned.
IN_MEM_BURST_LENGTH_CH5

Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes
IN_PAGE_BOUND_EN_CH5

Set this bit to 1 to make sure AXI write data don’t cross the address boundary which define by mem_burst_length
IN_RST_CH5

Write 1 then write 0 to this bit to reset Rx channel
IN_CMD_DISABLE_CH5

Write 1 before reset and write 0 after reset

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data